1. Field of the Invention
The present invention relates generally to device processing of Silicon-On-Insulator (SOI) wafers, and more particularly, relates to a method of forming a frontside contact to the silicon substrate of a SOI wafer.
2. Description of the Prior Art
SOI Technology has been shown to provide many advantages over bulk silicon technology. These advantages include higher speed, lower power and resistance to certain forms of radiation.
In many applications it is desirable to ground or bias the bottom substrate of a SOI circuit. In order to make an electrical connection at the backside of the wafer it requires additional wafer processing. In most of the more advanced packaging technologies such as flip chip and die stacking, making a connection to substrate silicon via the back of the die is cost prohibitive. Therefore, connecting the substrate to a standard topside metallization pad is necessary. However, the challenge of forming this contact during normal processing flow without adding major requirements to the standard processes without this topside contact is significant. This is especially true in the presence of highly planarized contact dielectric processes (i.e. Chemical Mechanical Polishing (CMP) and photoresist planarized contacts) required for today's deep submicron lithography where the thickness of the contact dielectric over the substrate contact may be in the range of 0.2 to 1.0 micron more than the thickness over the thickest region in the normal circuit area, which would typically be the source/drain contact areas. Scaling designs into the deep submicron range normally requires a high degree of planarity in the contact dielectric in order to be able to lithographically define contact and metal interconnect layers. Even without a frontside contact to the substrate, the selectivity of the contact etch is already required to be quite high. In the prior art, in order to make simultaneous contact to gate polysilicon, source and drain regions, and the underlying substrate, the selectivity of contact etch to gate polysilicon must be increased significantly in order to be able to etch the planarized contact dielectric all the way down to the silicon substrate.
Brady, et al, in U.S. Pat. No. 5,314,841, "Method of Forming a Frontside Contact to the Silicon Substrate of a SOI Wafer" describes a frontside contact formation process. This prior art has the weakness of increasing the etch selectivity requirements of the process significantly when compared to a process that does not include the frontside substrate contact.
It is therefore an object of the present invention to provide a frontside substrate contact without significantly increasing the selectivity requirements of the etch of the planarized contact dielectric.
It is another object of the present invention to teach a simple method to create a sloped oxide edge using reflowed photoresist with an oxide etch non-selective to photoresist.